Taking control of data centres is a low-RISC move
In the early 1990s, each passing year seemed to bring a new CPU architecture. Exotic chips such as Hobbit, PA-RISC, MIPS, Sparc, PowerPC and Alpha were all ready to steal the crown from Intel’s x86 architecture, taking over the desktop one machine at a time.
Of course, it never happened. Unix workstations did deploy a range of powerful 64-bit reduced instruction set (RISC) CPU designs, but they remained firmly stuck at the extreme high-end of computing, with only PowerPC, co-designed by Apple, IBM and Motorola, ever remotely troubling the desktop market.
Today, the two dominant CPU families are the 64-bit iteration of x86 on the desktop (let’s not speak of the fate of Itanium), and Arm in mobile devices. There is a new kid on the block, though, and it wears its RISC design on its sleeve: RISC-V.
Several significant CPU companies are already firing out RISC-V silicon. For instance, Imagination (which bought MIPS Technologies, the company that created the CPUs once used in the powerful workstations and supercomputers of the late, lamented Silicon Graphics) is all-in on RISC-V. Intel, for its part, is playing hokey-cokey, having closed its Pathfinder system on a chip (SoC) initiative this year, only six months after launching it.
Today, RISC-V is already common in microcontrollers and embedded systems but the CPU’s designers have grander ambitions. Although it is unlikely to trouble the desktop any time soon (though a first laptop has appeared), the RISC-V International Association, the non-profit that controls the architecture’s intellectual property has its sights set on the data centre.
Like Arm, RISC-V offers a low price-per-watt equation, something that will only become more important as demand for compute grows in the face of rising use of artificial intelligence (AI) applications, not to mention concerns about sustainability in the data centre.
In order for RISC-V to get there, new, more powerful CPUs are required. That does only seem to be a question of time, however: what is most interesting about RISC-V is that its instruction set is open source. In practice, this means, unlike, say, creating an Arm design, which requires the purchase of an expensive licence, any semiconductor designer can create and control its own RISC-V silicon.
Of course, then there is China. Locked in a trade cold war with the US, China has clearly telegraphed its desire to be less dependent on the West for core technologies such as CPUs. In practice, this resulted in 2022’s crackdown on ‘soft’ tech such as e-commerce and app development, which was a clear signal that the Chinese government wanted investment to flow into deep technology rather than consumer products.
China already has its own native CPU and instruction set in the form of Loongson, which is derived from MIPS, but convincing companies in other countries to use it has proved an uphill battle. RISC-V, with its open designs, would be another story altogether.
Similarly, India’s ministry of electronics and IT has launched the Digital India RISC-V initiative, with the goal of debuting a native Indian CPU family next year.
National technological sovereignty is not the only factor working in RISC-V’s favour, though. The open nature of the instruction set means that companies can design their own silicon, ensuring they have total control of it, but do so without having to start from a blank sheet of paper.
At the same time, as processing power has grown, the need for applications to be coded near silicon level in assembler has faded, creating space for alternative CPU architectures outside of niche applications. Indeed, with virtualisation and emulation so widespread today, the compatibility barriers to introducing a new architecture are lower than ever. As a result, RISC-V is well worth keeping an eye on.
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